FIG. 1 shows a prior art bus 120. A bus 120 is a “shared medium” communication structure that is used to transport communications between electronic components 101a-10Na and 110a, where N is an integer. Shared medium means that the components 101a-10Na and 110a that communicate with one another physically share and are connected to the same electronic wiring 120. That is, wiring 120 is a shared resource that is used by any of components 101a-10Na and 110a to communicate with any other of components 101a-10Na and 110a. For example, if component 101a wished to communicate to component 10Na, component 101a would send information along wiring 120 to component 10Na; if component 103 wished to communicate to component 110a, component 103a would send information along the same wiring 120 to component to component 110a, etc.
Computing systems have traditionally made use of busses. For example, with respect to certain IBM compatible PCs, bus 120 corresponds to a PCI bus where components 101a-10Na correspond to “I/O” components (e.g., LAN networking adapter cards, MODEMS, hard disk storage devices, etc.) and component 110a corresponds to an I/O Control Hub (ICH). As another example, with respect to certain multiprocessor computing systems, bus 120 corresponds to a “front side” bus where components 101a-10Na correspond to microprocessors and component 110a corresponds to a chipset.
Owing to an artifact referred to as “capacitive loading”, busses are less and less practical as computing system speeds grow. Basically, as the capacitive loading of any wiring increases, the maximum speed at which that wiring can transport information decreases. That is, there is an inverse relationship between a wiring's capacitive loading and that same wiring's speed. Each component that is added to a wire causes that wire's capacitive loading to grow. Thus, because buses typically couple multiple components, bus wiring 120 is typically regarded as being heavily loaded with capacitance.
Computing systems are migrating to a “link-based” component-to-component interconnection scheme. FIG. 2 shows a comparative example vis-à-vis FIG. 1. According to the approach of FIG. 2, computing system components 101b-10Nb and 110b are interconnected through a mesh 140 of high speed uni-directional point-to-point links 1301 through 130N. A pair of uni-directional links typically comprises a first unidirectional point-to-point link that transmits information in a first direction and a second unidirectional point-to-point link that transmits information is a second direction that is opposite that of the first direction. Because a unidirectional point-to-point link typically has a single endpoint, its capacitive loading is substantially less than that of a shared media bus.
Each point-to-point link can be constructed with copper or fiber optic cabling and appropriate drivers and receivers (e.g., single-ended or differential line drivers and receivers for copper based cables; and LASER or LED E/O transmitters and O/E receivers for fiber optic cables, etc.). Mesh 140 observed in FIG. 2 is simplistic in that each component is connected by a point-to-point link to every other component. In more complicated schemes, mesh 140 is a network having routing/switching nodes in order to transport information from a source component to a destination component. Depending on the implementation, the routing/switching function may be a stand-alone function within the mesh network or may be integrated into a substantive component of the computing system (e.g., processor, memory controller, I/O unit, etc.).